Cadence has announced that its complete PCIe 6.0 subsystem, combining PHY and controller IP, has achieved first-pass compliance with the PCI Express 6.0 specification.
The x8 subsystem was tested at the standard’s full 64 GT/s data rate during PCI-SIG’s first official PCIe 6.0 compliance workshop in late July. Built on TSMC’s N3 process, the solution passed all required PCIe 6.0 compliance tests and has been added to the PCI-SIG Integrators List.
The milestone is significant for AI and high-performance computing systems, where PCIe is used to connect accelerators, network interfaces, and storage devices. PCIe 6.0 doubles the data rate of PCIe 5.0 to 64 GT/s, providing the bandwidth needed for increasingly data-intensive workloads.
Cadence said it worked with PCI-SIG, test equipment providers, and other industry partners ahead of the official workshop to conduct interoperability testing and address potential issues before formal compliance testing.
The company also highlighted several aspects of its PCIe 6.0 implementation, including ADC- and DSP-based equalization, firmware-optimized SerDes operation and support for multiple protocols. With the subsystem designed with power efficiency in mind and incorporating the latest PCI-SIG engineering change notices, the solution has also been licensed by Positron AI for use in an AI inference accelerator chip.
Positron AI said the silicon implementation and interoperability testing provide confidence that the interface can support the high-bandwidth requirements of its transformer workloads.
With compliance testing completed, Cadence’s complete PCIe 6.0 subsystem is now available for SoC providers to integrate into their designs. The company also offers PCIe technology solutions extending up to the PCIe 7.0 specification.
