Cadence has recently worked out a new deal with Samsung Foundry that pushes their existing partnership to a new high, as they focus on 2nm chip design for AI-heavy workloads, starting from concept to deliverable products, especially as designs get more complex with AI, HPC, and 3D-IC integration.
For Cadence, they are expanding their Memory and Interface IP portfolio on Samsung’s second-generation 2nm process, and that includes support for high-speed interconnects like PCIe, UCIe, SerDes, and even NVIDIA’s NVLink-C2C ecosystem. On top of that, they’re tightening integration with GPU-accelerated workflows, which is basically about using compute-heavy tools to speed up chip design itself, not just the chips being built.
A full stack of EDYA and system design will flow into a certified state that includes tools like Innovus for implementation, Virtuoso for analog and custom design, and their 3D-IC platform for multi-die system design. The key angle here is sign-off confidence, meaning engineers can trust the simulation, timing, power, and verification results enough to move to manufacturing without last-minute surprises.
In practical terms, this is about AI-assisted optimization in chip design – automatically exploring design choices, tuning performance, power, and area tradeoffs, and reducing iteration cycles that normally slow down tapeout.
NVIDIA comes into the picture through NVLink-C2C and CUDA-X accelerated workflows as part of the broader push for high-bandwidth AI infrastructure, which is especially relevant for data centers running large AI models and distributed compute systems.
Meanwhile, companies like Ambarella are already using the platform direction for next-generation edge AI chips. Their focus is on ultra-low-power perception systems for robotics, drones, and autonomous devices, where efficiency per watt matters as much as raw performance. The key takeaway there is that this isn’t just about data center chips, but also about pushing advanced node design into edge environments.
Zooming out, the partnership is really about tightening the entire semiconductor pipeline at 2nm – from IP, to tools, to system-level design – so that building AI-capable silicon becomes less fragmented and more predictable. As chip complexity climbs, especially with 3D stacking and heterogeneous integration, the goal is to reduce risk while speeding up time to tapeout.
