Designing a chip is one of the most complex engineering jobs out there, and Cadence is betting that general-purpose AI isn’t specialized enough to do it well. Therefore, they have announced the Maestro AI Model Portfolio, a family of domain-specialized models that power its AI Super Agents across semiconductor and system design.
The portfolio spans multiple model sizes and architectures, mixing domain-specialized post-trained large language models, trained decision models, and self-improving agent skills. It works with the AuraStack, ChipStack, InnoStack, and ViraStack AI Super Agents, which blend frontier, open-weight, and domain-specialized models across cloud and on-premises environments. Give an agent a high-level objective, and it interprets the design intent, breaks the work into tasks, coordinates Maestro with other leading models, and drives the EDA and SDA tools. Along the way, it analyzes results and weighs trade-offs against engineering requirements, cost, and security. Customers can post-train the models, including NVIDIA Nemotron, on their own proprietary data, designs, and workflows, and balancing tool calls with LLM calls significantly cuts token use.
Initial performance benchmarks show up to 30% improvement in quality of results and up to 5X greater token efficiency compared with a general-purpose foundation model. Cadence credits a vertically integrated learning environment that combines its domain knowledge, curated engineering datasets, AI Super Agents, tools, and evaluation harnesses. Its deterministic solvers check outputs against engineering objectives, constraints, and ground truth, creating verified feedback loops for reinforcement learning.
For security-conscious teams, the whole environment can run on Cadence’s secure cloud, secure public clouds, or in a customer-controlled on-premises setup, and Cadence and NVIDIA are working on agent security through the NVIDIA OpenShell Reference Architecture.
The first Maestro models will be available to select early access customers in Q4 of 2026.
